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NCP1601A, NCP1601B Compact Fixed Frequency Discontinuous or Critical Conduction Voltage Mode Power Factor Correction Controller
The NCP1601 is a controller designed for Power Factor Correction (PFC) boost circuits. The device operates in fixed-frequency Discontinuous Conduction Mode (DCM) and variable-frequency Critical Conduction Mode (CRM) and takes advantages from both operating modes. DCM limits the maximum switching frequency. It simplifies the front-ended EMI filter design. CRM limits the maximum currents of the boost stage diode, MOSFET and inductor. It reduces the costs and improves the reliability of the circuit. This device substantially exhibits unity power factor while operating in DCM and CRM. The NCP1601 minimizes the required number of external components. It incorporates high safety protection features that make the NCP1601 suitable for robust and compact PFC stages.
Features
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8 8 1 SOIC-8 D SUFFIX CASE 751 1 1601x ALYW G
8 PDIP-8 N SUFFIX CASE 626 1 1 NCP1601x AWL YYWWG
8
* * * * * * * * * * * * * * *
Near-Unity Power Factor in DCM or CRM Voltage-Mode Operation Low Startup and Shutdown Current Consumption Programmable Switching Frequency for DCM Synchronization Capability Overvoltage Protection (107% of Nominal Output Level) Undervoltage Protection or Shutdown (8% of Nominal Output Level) Programmable Overcurrent Protection Thermal Shutdown with Hysteresis (95/140C) Two VCC Undervoltage Lockout Hysteresis Options: 4.75 V for NCP1601A and 1.5 V for NCP1601B Pb-Free Packages are Available
x A L, WL Y, YY W, WW G G
= A or B = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package = Pb-Free Package
PIN CONNECTIONS
FB 1 Vcontrol 2 Ramp 3 CS 4 (Top View) 8 VCC 7 Drv 6 GND 5 Osc
Typical Applications
Electronic Light Ballast AC Adapters TV & Monitors Mid-Power Applications
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2005
1
December, 2005 - Rev. 4
Publication Order Number: NCP1601A/D
NCP1601A, NCP1601B
AC Input
EMI Filter
Output
15 V FB VCC Vcontrol Drv Ramp GND CS Osc NCP1601X
Figure 1. Typical Application Circuit
L Output Voltage (Vout)
AC Input
EMI Filter
Cfilter RCS
Cbulk on off
RFB
IS IFB Vcontrol
1
FB / SD VCC 9V
Current Mirror VCC(on) / 9 V
V reg
2
300 k
+ -
Vcontrol Processing 9V C1 R2 1 C3 R3 Ccontrol
96% I ref
I ref I FB
VCC
8
18 V
+ -
Regulation Block UVLO R1 Overvoltage Protection (IFB > 107% Iref) Shutdown / UVP (IFB < 8% Iref) Zero Current Detection (IS < 14 mA) 0
VCC RS
& &
- +
Reference Block Internal Bias CS
Vton
3.9 Vmax clamp
PFC Modulation Ich Thermal Shutdown (95 / 140 C) OR Ramp
4
9V Osc / Sync
Current Mirror
Overcurrent Protection (IS > 203 mA)
3
1 0 9V Cramp
45 mA
5
COSC 9V 0 1 94 mA
+ -
VCC
&
S R delay Q
R Drv S Q Output Driver
5 / 3.5 V
7
GND
6
Oscillator / Synchronization Block
Figure 2. Functional Block Diagram
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NCP1601A, NCP1601B
PIN FUNCTION DESCRIPTION
Pin 1 Symbol FB Function Feedback / Shutdown Function This pin receives a current IFB which is proportional to the PFC circuit output voltage. The current is for the output regulation, output Overvoltage Protection (OVP), and output undervoltage protection (UVP). When IFB goes above 107% Iref, OVP is activated and the Drive Output is disabled. When IFB goes below 8% Iref, the device enters a low-current consumption shutdown mode. The voltage of this pin Vcontrol directly controls the input impedance and hence the power factor of the circuit. This pin is connected to an external capacitor to limit the control voltage Vcontrol bandwidth typically below 20 Hz to achieve Power Factor Correction. This pin is connected to an external capacitor to set a ramp signal. The capacitor value directly affects the input impedance of the PFC circuit and hence the maximum input power. This pin sources a current IS which depends on the inductor current and an offset voltage. The current is for Overcurrent Protection (OCP) and zero current detection. When IS is above 200 mA, OCP is activated and the Drive Output is disabled. When IS is below 14 mA, the circuit detects a zero current. This information is used by the on-time modulation arrangement and by the oscillator block. In oscillator mode, this pin is connected to an external capacitor to set the oscillator frequency of the DCM operation. In synchronization mode, this pin is connected to an external driving signal. The positive edge of the drive output is synchronized to the negative edge of the external signal in DCM operation. If the inductor current is non-zero at the end of a switching period, the output drive is not allowed to turn on. CCM operation is prohibited. Instead, the circuit operates in CRM in this case. - This pin provides an output to an external MOSFET. This pin is the positive supply of the device. The operating range is between 9 V and 18 V with UVLO start threshold 13.75 V for NCP1601A and 10.5 V for NCP1601B.
2
Vcontrol
Control
3 4
Ramp CS
Ramp Current Sense
5
Osc
Oscillator / Synchronization
6 7 8
GND Drv VCC
The IC ground Drive Output Supply Voltage
MAXIMUM RATINGS
Rating FB, Vcontrol, Ramp, CS, Osc Pins (Pins 1-5) Maximum Voltage Range Maximum Current Drive Output (Pin 7) Maximum Voltage Range Maximum Current Range (Note 2) Power Supply Voltage (Pin 8) Maximum Voltage Range Maximum Current Power Dissipation and Thermal Characteristics P suffix, Plastic Package, Case 626 Maximum Power Dissipation @ TA=70 C Thermal Resistance, Junction-to-Air D suffix, Plastic Package, Case 751 Maximum Power Dissipation @ TA=70 C Thermal Resistance, Junction-to-Air Operating Junction Temperature Range Storage Temperature Range Symbol Vmax Imax Vmax Imax Vmax Imax Value -0.3 to +9 100 -0.3 to +18 -500 to +750 -0.3 to +18 100 Unit V mA V mA V mA
PD RqJA PD RqJA TJ Tstg
800 100 450 178 -40 to +125 -65 to +150
mW C/W mW C/W C C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. A. This device series contains ESD protection and exceeds the following tests: Pins 1-8: Human Body Model 2000 V per MIL-STD-883, Method 3015. Machine Model Method 200 V. B. This device contains Latchup protection and exceeds 100 mA per JEDEC Standard JESD78. 1. Guaranteed by design.
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NCP1601A, NCP1601B
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25C. For min/max values, TJ = -40C to +125C, VCC = 15 V,
Vcontrol = 100 nF, Ramp = 100 pF, Osc = 220 pF unless otherwise specified) Characteristic OSCILLATOR Oscillator Frequency (Osc = 220 pF to GND) Internal Capacitance of the Oscillator Pin Maximum Oscillator Switching Frequency Oscillator Discharge Current (Osc = 5.5 V) Oscillator Charge Current (Osc = 3 V) Comparator Lower Threshold (Osc = 220 pF to GND) (Note 3) Comparator Upper Threshold (Osc = 220 pF to GND) Synchronization Pulse Width for Detection Synchronization Propagation Delay GATE DRIVE Gate Drive Resistor Output High and Draw 100 mA out of Drv Pin (Isource = 100 mA) Output Low and Insert 100 mA into Drv Pin (Isink = 100 mA) Gate Drive Rise Time from 1.5 V to 13.5 V (Drv = 1 nF to GND) Gate Drive Fall Time from 13.5 V to 1.5 V (Drv = 1 nF to GND) 7 ROH ROL 7 7 tr tf Iref IregL / Iref Rcontrol Vcontrol(max) VFB1 IOVP / Iref IOVP IUVP / Iref VS IS(OCP) VS(OCP) IS(ZCD) VS(ZCD) RS(ZCD) Ich Rpower Vton(max) Cramp(int) Rramp TSD TH 5 2 - - 11.6 7.2 53 32 20 18 - - W W ns ns mA % kW V V % mA % 5 5 5 5 5 5 5 5 5 fosc Cosc(int) fosc(max) Iodch Ioch Vsync(L) Vsync(H) tsync(min) tsync(d) 52 - - 40 40 3.0 4.5 500 - 58 36 405 49 45 3.5 5 - 371 64 - - 60 60 4.0 5.5 - - kHz pF kHz mA mA V V ns ns Pin Symbol Min Typ Max Unit
FEEDBACK / OVERVOLTAGE PROTECTION / UNDERVOLTAGE PROTECTION Reference Current Regulation Block Ratio Vcontrol Pin Internal Resistor Maximum Control Voltage (IFB = 100 mA) Feedback Pin Voltage (IFB = 100 mA) Overvoltage Protection Current Ratio Overvoltage Protection Current Undervoltage Protection Current Ratio CURRENT SENSE Current Sense Pin Offset Voltage (IS = 100 mA) Overcurrent Protection Level Current Sense Pin Offset Voltage at Overcurrent Level Zero Current Detection Level Current Sense Pin Offset Voltage at Zero Current Level Zero Current Sense Resistor (RS(ZCD) = VS(ZCD) / IS(ZCD)) RAMP Charging Current (Ramp = 0 V) Maximum Power Resistance (Rpower = Vcontrol(max) / Ich) Internal Clamping of Voltage Vton Internal Capacitance of the Ramp Pin Ramp Pin Sink Resistance (Osc = 0 V, Ramp = 1 mA sourcing) THERMAL SHUTDOWN Thermal Shutdown Threshold (Note 4) Thermal Shutdown Hysteresis 2. Comparator lower threshold is also the synchronization threshold. 3. Guaranteed by design. - - 140 - - 45 - - C C 3 3 - 3 3 95 9.5 - - - 100 10.5 3.9 20 71.5 105 11.5 - - - mA kW V pF W 4 4 4 4 4 4 - 190 0 9 0 - 4 203 3.2 14 7.5 0.536 - 210 20 19 20 1 mV mA mV mA mV kW 1 1 2 2 1 1 1 1 192 95 - 0.95 - 104 - 4 203 96 300 1.05 3 107 217 8 208 97 - 1.15 - - 225 15
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NCP1601A, NCP1601B
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25C. For min/max values, TJ = -40C to +125C, VCC = 15 V,
Vcontrol = 100 nF, Ramp = 100 pF, Osc = 220 pF unless otherwise specified) Characteristic SUPPLY SECTION Startup Threshold (UVLO) - NCP1601A Startup Threshold (UVLO) - NCP1601B Minimum Voltage for Operation After Turn-On UVLO Hysteresis - NCP1601A UVLO Hysteresis - NCP1601B Power Supply Current: Startup (VCC = VCC(on) - 0.2 V) Operating (VCC = 15 V, Drv = open, Osc = 220 pF) Operating (VCC = 15 V, Drv = 1 nF to GND, Osc = 220 pF) Shutdown (VCC = 15 V, IFB = 0 A) 8 8 8 8 Istup ICC1 ICC2 Istdn - - - - 17 2.7 3.7 24 40 5 5 50 mA mA mA mA VCC(on) VCC(off) VCC(H) 12.5 9.6 8.25 4 1 13.75 10.5 9 4.75 1.5 15 11.4 9.75 - - V V V V V Pin Symbol Min Typ Max Unit
TYPICAL CHARACTERISTICS
60 fOSC, OSCILLATOR FREQUENCY (kHz) 59 58 57 56 55 54 53 52 51 50 -50 -25 0 25 50 COSC = 220 pF 75 100 125 OSCILLATOR CHARGE & DISCHARGE CURRENT (mA) 51 50 Iodch osc pin = 5.5 V 49 48 47 46 Ioch osc pin = 3 V 45 44 -50
-25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 3. Oscillator Frequency vs. Temperature
Figure 4. Oscillator Charge and Discharge Current vs. Temperature
18 GATE DRIVE RESISTANCE (W)
5.5 OSCILLATOR COMPARATOR THRESHOLDS (V) Vsync(H) 5.0
16 14 12 10 8 6 4 2 0 -50 -25 0 25 50 75 100 125 ROL ROH
4.5 COSC = 220 pF 4.0 Vsync(L)
3.5
3 -50
-25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 5. Oscillator Comparator Thresholds vs. Temperature
Figure 6. Drive Output Resistance vs. Temperature
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NCP1601A, NCP1601B
TYPICAL CHARACTERISTICS
210 IREF, REFERENCE CURRENT (mA) Vcontrol, CONTROL VOLTAGE (V) 208 206 204 202 200 198 196 194 192 190 -50 -25 0 25 50 75 100 125 1.2 1.0 0.8 TJ = -40C 0.6 0.4 0.2 0 150 TJ = 25C TJ = 125C
160
170
180
190
200
210
220
TJ, JUNCTION TEMPERATURE (C)
IFB, FEEDBACK CURRENT (mA)
Figure 7. Reference Current vs. Temperature
100 REGULATION BLOCK RATIO (%) 99 98 97 96 95 94 93 92 91 90 -50 -25 0 25 50 75 100 125 MAXIMUM CONTROL VOLTAGE (V) 1.10
Figure 8. Regulation Block Transfer Function
1.08
1.06
1.04
1.02 IFB = 100 mA 1.00 -50 -25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 9. Regulation Block Ratio vs. Temperature
Figure 10. Maximum Control Voltage vs. Temperature
OVERVOLTAGE PROTECTION RATIO (%) 110 109.5 109 108.5 108 107.5 107 106.5 106 105.5 105 -50 -25 0 25 50 75 100 125
6 FEEDBACK PIN VOLTAGE (V) 5 TJ = 125C 4 3 TJ = -40C 2 1 0 0 50 100 150 200 250 IFB, FEEDBACK PIN CURRENT (mA) TJ = 25C
TJ, JUNCTION TEMPERATURE (C)
Figure 11. Feedback Pin Voltage vs. Feedback Current
Figure 12. Overvoltage Protection Ratio vs. Temperature
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NCP1601A, NCP1601B
TYPICAL CHARACTERISTICS
UNDERVOLTAGE PROTECTION RATIO (%) 220 OVERVOLTAGE THRESHOLD (mA) 218 216 214 212 210 208 206 204 202 200 -50 -25 0 25 50 75 100 125 10 9 8 7 6 5 4 3 2 1 0 -50 -25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 13. Overvoltage Protection Threshold vs. Temperature
120 CS PIN OFFSET VOLTAGE (mV) 100 80 60 40 20 0 0 50 100 150 200 250 IS, CS PIN CURRENT (mA) TJ = 125 C TJ = 25 C TJ = -40 C CS PIN OFFSET VOLTAGE (mV) 10 9 8 7 6 5 4 3 2 1
Figure 14. Undervoltage Protection Ratio vs. Temperature
VS(ZCD)
VS(OCP)
0 -50
-25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (C)
Figure 15. CS Pin Offset Voltage vs. Current
OVERCURRENT PROTECTION LEVEL (mA)
Figure 16. CS Pin Offset Voltage at OCP, ZCD vs. Temperature
ZERO CURRENT DETECTION LEVEL (mA) 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 -50 -25 0 25 50 75 100 125
210 208 206 204 202 200 198 196 194 192 190 -50 -25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 17. Overcurrent Protection Level vs. Temperature
Figure 18. Zero Current Detection Level vs. Temperature
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NCP1601A, NCP1601B
TYPICAL CHARACTERISTICS
ZERO CURRENT SENSE RESISTOR (W) 700 ICH, CHARGING CURRENT (mA) 0 25 50 75 100 125 600 500 400 300 200 100 0 -50 105 104 103 102 101 100 99 98 97 96 95 -50 -25 0 25 50 75 100 125
-25
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 19. Zero Current Sense Resistor vs. Temperature
12.0 MAXIMUM POWER RESISTANCE (kW) VCC UNDERVOLTAGE LOCKOUT THRESHOLDS (V) 11.5 11.0 10.5 10.0 9.5 9.0 -50 15
Figure 20. Charging Current vs. Temperature
VCC(on) for NCP1601A 14 13 12 11 10 VCC(off) 9 8 -50 VCC(on) for NCP1601B
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 21. Maximum Power Resistance vs. Temperature
35 VCC SUPPLY CURRENT WITH 1.0 nF LOAD AND WITHOUT LOAD (mA) 30 25 20 15 10 5 0 -50 Istup Istdn 4 3.8 3.6 3.4 3.2 3 2.8 2.6 2.4 2.2 2 -50
Figure 22. Supply Voltage Undervoltage Lockout Thresholds vs. Temperature
VCC SUPPLY CURRENT IN STARTUP AND SHUTDOWN MODE (mA)
ICC2, 1 nF Load
ICC1, No Load VCC = 15 V, COSC = 220 pF -25 0 25 50 75 100 125
-25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 23. Supply Current in Startup and Shutdown Mode vs. Temperature
Figure 24. Supply Current vs. Temperature
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NCP1601A, NCP1601B
FUNCTIONAL DESCRIPTION
Introduction
The NCP1601 is a Power Factor Correction (PFC) boost controller designed to operate in Discontinuous Conduction Mode (DCM) and Critical Conduction Mode (CRM). The fixed-frequency nature of DCM limits the maximum switching frequency. It limits the possible conducted and radiated EMI noise that may pollute surrounding systems. NCP1601 offers the simplest solution to PFC including fewer external circuit components and simple voltage-mode feedback. The diode turn-off switching loss is negligible and hence there is no need to use a low reverse-recovery time trr diode. On the other hand, the CRM feature is added to limit the maximum current stress to twice of the average current. The NCP1601 incorporates high safety protection features and combines the advantages of DCM and CRM so that the NCP1601 is suitable for robust and compact PFC stages. The NCP1601 provides the following protection features: 1. Overvoltage Protection (OVP) is activated and the output drive goes low when the output voltage exceeds 107% of the nominal regulation level which is a user-defined value. The circuit automatically resumes operation when the output voltage becomes lower than 107%. 2. Undervoltage Protection (UVP) is activated and the device is shut down when the output voltage goes below 8% of the nominal regulation level. The circuit automatically resumes operation when the output voltage goes above 8% of the nominal regulation level. This feature also provides output open-loop protection and external shutdown feature. 3. Overcurrent Protection (OCP) is activated and the output device goes low when the inductor current exceeds a user-defined value. The operation automatically resumes when the inductor current becomes lower than this user-defined value at the next clock cycle. 4. Thermal Shutdown (TSD) is activated and the output drive is disabled when the junction temperature exceeds 140C. The operation resumes when the junction temperature falls down by typical 45C. The NCP1601 is available in two versions. The NCP1601A has a typical 4.75 V undervoltage lockout (UVLO) hysteresis, while NCP1601B has a typical 1.5 V UVLO hysteresis. It allows the use of different VCC biasing schemes.
Operating Modes of NCP1601
conditions, CRM can be an alternative option which is without power factor degradation. On the other hand, the NCP1601 can be viewed as a CRM controller with a frequency clamp (maximum switching frequency limit) alternative option which is also without power factor degradation. In summary, the NCP1601 can cover both CRM and DCM without power factor degradation. Based on the selections of the boost inductor and the oscillator frequency, the circuit is capable of the following three applications. 1. "Mostly in CRM" with a frequency clamp set by the oscillator or synchronization frequency. 2. "Mostly in fixed-frequency mode DCM" and only run in CRM at high load and low line. 3. "Fixed-frequency DCM" only.
Current Inductor current, IL
Input current, Iin
time DCM Critical Mode DCM
Figure 25. Operating Modes
DCM needs higher peak inductor current comparing to CRM in the same averaged input current. Hence, CRM is generally preferred at around the sinusoidal peak for lower the maximum current stress but DCM is also preferred at the non-peak region to avoid excessive switching frequencies. Because of the variable-frequency feature of the CRM and constant-frequency feature of DCM, switching frequency is the maximum in the DCM region and hence the minimum switching frequency will be found at the moment of the sinusoidal peak.
DCM PFC Circuit
The NCP1601 is a PFC driver primarily designed to operate in fixed-frequency DCM. In the most stressful
A DCM/CRM PFC boost converter is shown in Figure 26. Input voltage is a rectified 50 or 60 Hz sinusoidal signal. The MOSFET is switching at a high frequency (typically around 100 kHz) so that the inductor current IL basically consists of high-frequency and low-frequency components. Filter capacitor Cfilter is an essential and very small value capacitor in order to eliminate the high-frequency content of the DCM inductor current IL. This filter capacitor cannot
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NCP1601A, NCP1601B
be too bulky because it can pollute the power factor by distorting the rectified sinusoidal input voltage.
Iin Vin Cfilter IL L Vout Cbulk
Power factor is corrected when the input impedance Zin in (eq.3) are constant or slowly varying. The MOSFET on time t1 or PFC modulation duty is generated by a feedback signal Vton and a ramp. The PFC modulation circuit and timing diagram are shown in Figure 28. A relationship in (eq.4) is obtained.
t1 + Cramp Vton Ich
(eq.4)
Figure 26. DCM/CRM PFC Boost Converter PFC Methodology
Ramp 3 Cramp
Ich
NCP1601 uses a proprietary PFC methodology particularly designed for both DCM and CRM operation. The PFC methodology is described in this section.
Inductor Current
closed when output low
PFC Modulation + - Vton Turns off MOSFET
Vton ramp output Ipk
Figure 28. PFC Modulation Circuit and Timing Diagram
t1 t2 T t3 time
Figure 27. Inductor Current in DCM
As shown in Figure 27, the inductor current IL of each switching cycle starts from zero in DCM. CRM is a special case of DCM when t3 = 0. When the PFC boost converter MOSFET is on, the inductor current IL increases from zero to Ipk for a time duration t1 with inductance L and input voltage Vin. (eq.1) is formulated.
Ipk Vin + L t1
(eq.1)
The charging current Ich is constant 100 mA current and the ramp capacitor Cramp is constant for a particular design. Hence, according to (eq.4) the MOSFET on time t1 is proportional to Vton. In order to protect the PFC modulation comparator, the maximum voltage of Vton is limited to internal clamp Vton(max) (3.9 V typical) and the ramp pin (Pin 3) is with a 9 V ESD Zener diode. The 3.9 V maximum limit of this Vton indirectly limits the maximum on time.
closed when zero current R1 R2
The input filter capacitor Cfilter and the front-ended EMI filter absorb the high-frequency component of inductor current. It makes the input current Iin a low-frequency signal.
Ipk (t1 ) t2) Iin + 2T Ipk Iin + 2
Ccontrol for DCM (eq.2a)
C1 Vcontrol 2 - + R3 Vton C3
for CRM
(eq.2b)
Figure 29. Vcontrol Processing Circuit
From (eq.1) and (eq.2), the input impedance Zin is formulated.
V 2TL for DCM Zin + in + Iin t1(t1 ) t2) V 2L Zin + in + t1 Iin
for CRM (eq.3a)
The Vcontrol processing circuit generates Vton from control voltage Vcontrol and time information of zero inductor current. The circuit in Figure 29 makes (eq.5) where the value of resistor R1 is much higher than the value of resistor R2 (R1 >> R2).
Vton + T Vcontrol t1 ) t2
for DCM (eq.5a)
(eq.3b)
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NCP1601A, NCP1601B
Vton + Vcontrol
for CRM (eq.5b)
It is noted that Vton is always greater than or equal to Vcontrol (i.e., Vton Vcontrol). In summary, the input impedance Zin in (eq.6) is obtained from (eq.1)-(eq.5)
2 L Ich V Zin + in + Iin Cramp Vcontrol
(eq.6)
Rpower +
Vcontrol(max) 1.05 V + + 10.5 kW 100 mA Ich
(eq.9)
It means that the maximum input and output power (Pin(max) and Pout(max)) are limited to 10% variation.
Pin(max) + Vac2CrampRpower 2L hVac2CrampRpower 2L
(eq.10a)
Control voltage Vcontrol comes from the PFC output voltage Vout which is a slowly varying signal. The bandwidth of Vcontrol can be additionally limited by inserting an external capacitor Ccontrol to the Vcontrol pin (Pin 2) in Figure 28. The internal 300 kW resistor and the capacitor Ccontrol create a low-pass filter which has a bandwidth fcontrol in (eq.7). It is generally recommended to limit the bandwidth below 20 Hz to achieve power factor correction. Typical value of Ccontrol is 0.1 mF.
1 Ccontrol u 2p300kW fcontrol
(eq.7)
Pout(max) +
(eq.10b)
The maximum input current Iac(max) to deliver the maximum input power Pin(max) is also derived in (eq.11). The suffix ac stands for RMS value.
Iac(max) + Pin(max) VacCrampRpower + 2L Vac
(eq.11)
Output Feedback
If the bandwidth of Vcontrol is much less than the 50 or 60 Hz line frequency, the input impedance Zin is slowly varying or roughly constant. Then, the power factor correction is achieved in DCM and CRM.
Vreg
The output voltage Vout of the PFC circuit is sensed as a feedback current IFB flowing into the FB pin (Pin 1) of the device. The FB pin voltage VFB1 is typically less than 5 V referring to Figure 11. It is much lower than Vout which is typically 400 V. Therefore, VFB1 is generally neglected.
V * VFB1 V IFB + out [ out RFB RFB
(eq.12)
96% Iref
Iref IFB
300k
Regulation Block
2 Vcontrol
Vcontrol Processing Circuit
where RFB is the feedback resistor connected between the FB pin (Pin 1) and the output voltage referring to Figure 2. Then, the feedback current IFB represents the output voltage Vout and will be used in the output voltage regulation, Undervoltage Protection (UVP), and Overvoltage Protection (OVP).
Output Voltage Regulation
Ccontrol
Feedback current IFB, which presents output voltage Vout, is regulated with a reference current (Iref = 203 mA typical) as shown in Figure 31.
Vreg 1.05 V
Figure 30. Vcontrol Low-Pass Filtering Maximum Power
Input and output power (Pin and Pout) are derived in (eq.8) when the circuit efficiency h is obtained or assumed. The variable Vac stands for the RMS input voltage.
Vac2CrampVcontrol V2 Pin + ac + Zin 2LIch Pout + h Pin + hVac2CrampVcontrol 2LIch
(eq.8a)
96% Iref
Iref
IFB
Figure 31. Regulation Block
(eq.8b)
From (eq.8), control voltage Vcontrol controls the amount of output power, input power, or input impedance. The maximum value of the control voltage Vcontrol is 1.05 V (i.e., Vcontrol(max) = 1.05 V). A parameter called maximum power resistor Rpower (10.5 kW typical) is defined in (eq.9) and restricted to have a maximum 10% variation (i.e., 9.5 kW Rpower 11.5 kW) for defining the maximum power in an application.
When IFB is lower than 96% of Iref, the Vreg which is the output of the regulation block is as high as Vcontrol(max) (1.05 V typical) that gives the maximum value on Vton. As a result, it gives the maximum MOSFET on time and Vout increases. When IFB is higher than Iref, the Vreg becomes 0 V that gives no MOSFET on time and Vout decreases. As a result, the output voltage Vout is regulated around the range between 96% and 100% of the nominal value of RFB x Iref. Based on (eq.8) for a particular power level, the Vcontrol is inversely proportional to Vac2. Hence, in high Vac condition Vcontrol is lower. It means that IFB or output
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NCP1601A, NCP1601B
voltage is higher based on the regulation block characteristic in Figure 31. On the other hand, the Vcontrol in the low Vac condition is much higher than the high Vac condition. In order to not over-design the circuit in the application, the Vcontrol in the low Vac condition is usually very closed to Vcontrol(max). It makes the output voltage be almost 96% of the nominal value of RFB x Iref in low Vac condition while the output voltage is almost 100% of the nominal value RFB x Iref in high Vac condition. The feedback resistor RFB consists of two or three high precision resistors in order to set the nominal Vout precisely and safety purpose. The regulation block output Vreg is connected to control voltage Vcontrol through an internal resistor Rcontrol (300 kW typical) for the low-pass filter in Figure 30. The Vcontrol and the time information of zero current are collected in the Vcontrol processing circuit to generate Vton which is then compared to a ramp signal to generate the MOSFET on time t1 for power factor correction.
Overvoltage Protection (OVP)
IL
RS
IS
CS + VS -
NCP1601 Gnd
RCS
IL
Figure 32. Current Sensing
When the feedback current IFB is higher than 107% of the reference current Iref (i.e., the output voltage Vout is higher than 107% of its nominal value), the Drive Output pin (Pin 7) of the device goes low for protection and the switch of the Vcontrol processing circuit is kept off. The circuit automatically resumes operation when the output voltage is lower than 107%. The maximum OVP threshold is limited to 225 mA which corresponds to 225 mA x 1.95 MW + 5 V = 443.75 V when RFB = 1.95 MW (1.8 MW + 150 kW) and VFB1 = 5 V (for the worst case referring to Figure 11). Hence, it is generally recommended to use 450 V rating output capacitor to allow some design margin.
Undervoltage Protection (UVP)
Inductor current IL passes through RCS and creates a negative voltage. This voltage is measured by a current IS flowing out of the CS pin (Pin 4). The CS pin has an offset voltage VS. This offset voltage is studied in the setting of zero inductor current IL(ZCD) and the maximum inductor current IL(OCP) (i.e., overcurrent protection threshold). A typical variation of offset voltage VS versus sense current IS is shown in Figure 15. Higher the value of the offset voltage at low current region creates lower the zero current threshold for better accuracy. Based on Figure 32, (eq.13) is derived.
VS * RS IS + -RCS IL Zero Current Detection (ZCD)
(eq.13)
The device recognizes zero inductor current when the CS pin (Pin 4) sense current IS is lower than IS(ZCD) (14 mA typical). The offset voltage of the CS pin in this condition is VS(ZCD) (7.5 mV typical). It is illustrated in Figure 33. The inductor current IL(ZCD) at the ZCD condition is derived in (eq.14).
IL(ZCD) + RSIS(ZCD) * VS(ZCD) RCS
(eq.14)
When the feedback current IFB is lower than 8% of the reference current Iref (i.e., the output voltage Vout is lower than 8% of its nominal value), the device is shut down and consumes lower than 50 mA. In normal situation of boost converter configuration, the output voltage Vout is always higher than the input voltage Vin and the feedback current IFB is always higher than 8% of the reference current Iref. It enables the NCP1601 to operate. Hence, UVP happens when the output voltage is abnormally undervoltage, the FB pin (Pin 1) is opened, or the FB pin (Pin 1) is manually pulled low.
Current Sense
It is obvious that the IL(ZCD) is not always zero. In order to make it reasonably close to zero, the settings of RS and RCS are crucial.
VS RS > RS(ZCD)
Operating ZCD point RS = RS(ZCD) VS(ZCD) Ideal ZCD point IS IS(ZCD)
The device senses the inductor current IL by the current sense scheme in Figure 32. This scheme has the advantages of: (1) the inrush current limitation by the resistor RCS, and (2) the overcurrent protection and zero current detection implemented in the same pin.
Figure 33. CS Pin Characteristic when IL = 0
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12
NCP1601A, NCP1601B
Based on the CS pin (Pin 4) characteristics in Figure 15, Figure 33 is studied. When the inductor current is exactly zero (i.e., IL(ZCD) = 0), the ideal ZCD point in the Figure is reached where RS is RS(ZCD) (536 W typical). Considering the tolerance, the actual sense resistor RS is needed to be higher than the ideal value of RS(ZCD) to ensure that zero current signal is generated when sense current is smaller than the ZCD threshold (i.e., IS < IS(ZCD)). That is,
VS(ZCD) RS u RS(ZCD) + IS(ZCD)
(eq.15)
When overcurrent protection threshold is reached, the Drive Output of the device goes low.
Oscillator / Synchronization Block
Oscillator Clock 45 mA Osc 5 94 mA 0 + - 5 V/3.5 V 1 Zero Current Turn on MOSFET
SQ R
&
delay
The higher value of RS makes the longer distance between the operating and ideal ZCD points in Figure 33. Hence, RS has to be as low as possible. The best recommended value of RS is therefore the maximum of RS(ZCD) which is 1 kW. Now that the RS is set at a particular value which is greater than RS(ZCD). From (eq.13), the operating lines in (eq.16) with different inductor currents IL of (eq.13) are studied.
VS + RS * RCSIL
(eq.16)
Figure 35. Oscillator / Synchronization Block
clock clock edge (latch set signal) clock latch (latch output) inductor current time Discontinuous mode Critical mode
These operating lines are added in Figure 33 to formulate Figure 34. When the inductor current IL is lower than IL(ZCD), the sense current IS is lower than IS(ZCD) and hence the zero current signal is generated.
VS IL = 0
Figure 36. Oscillator Block Timing Diagram
IL = IL(ZCD)
IL > IL(ZCD)
Best ZCD point
VS(ZCD)
IS IS(ZCD) Operating ZCD point
The NCP1601 is a DCM / CRM PFC controller. In order to keep the operation in DCM or CRM only, the Drive Output cannot turn on as long as there is some inductor current flowing through the circuit. Hence, the zero current signal is provided to the oscillator / synchronization block in Figure 35. An input comparator monitors the Osc pin (Pin 5) voltage and generates a clock signal. The negative edge of the clock signal is stored in a RS latch. When zero current is detected, the RS latch will be reset and a set signal is sent to the output drive latch which turns on the MOSFET in the PFC boost circuit. Figure 36 illustrates a typical timing diagram of the oscillator block.
Oscillator Mode
Figure 34. CS Pin Characteristic with Different Inductor Current
It is noted in Figure 34 and (eq.16) that when the (RCS IL) term is smaller the error or distance between the lines to the line IL = 0 is smaller. Therefore, the value of the current sense resistor RCS is also recommended to be as small as possible to minimize the error in the zero current detection.
Overcurrent Protection (OCP)
The Osc pin (Pin 5) is connected to an external capacitor Cosc. When the voltage of this pin is above Vsync(H) (5 V typical), the pin sinks a current Iodch (94 - 45 = 49 mA typical) and the external capacitor Cosc discharges. When the voltage reaches Vsync(L) (3.5 V typical), the pin sources a current Ioch (45 mA typical) and the external capacitor Cosc is charged. It is noted that there is a typical 300 ns propagation delay and the 3.5 V and 5 V threshold conditions are measured on 220 pF Cosc capacitor. Hence, the actual oscillator hysteresis is a slightly smaller.
Osc pin voltage Osc clock Clock edge Drive output (DCM) 5V 3.5 V
Overcurrent protection is reached when IS is higher than IS(OCP) (200 mA typical). The offset voltage of the CS pin is VS(OCP) (3.2 mV typical) in this condition. That is
IL(OCP) + RSIS(OCP) * VS(OCP) RCS
(eq.17)
Figure 37. Oscillator Mode Timing Diagram in DCM http://onsemi.com
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NCP1601A, NCP1601B
There is an internal capacitance Cosc(int) (36 pF typical) in the oscillator pin and the oscillator frequency is to fosc(max) (405 kHz typical) when the Osc pin is opened. Hence, the oscillator switching frequency can be formulated in (eq.18) and represented in Figure 38.
Cosc +
700
C osc , Oscillator Capacitor (pF)
signal turns to 3.5 V. A timing diagram of synchronization mode is summarized in Figure 39.
5V 3.5 V
Sync Signal Osc Clock Clock Edge Drive Output (DCM)
36 pF @ 405 kHz * 36 pF fosc
(eq.18)
600 500 400 300 200 100 0 0 50 100 150 f osc , Oscillator Frequency (kHz) 200
Figure 39. Synchronization Mode Timing Diagram in DCM VCC Undervoltage Lockout (UVLO)
Figure 38. Osc Pin Frequency Setting Synchronization Mode
The Osc pin (Pin 5) receives an external digital signal with level high defined to be higher than Vsync(H) (5 V typical) and level low defined to be lower than Vsync(L) (3.5 V typical). An internal 9 V ESD Zener diode is connected to the Osc pin and hence the maximum synchronization voltage is 9 V. The circuit recognizes a synchronization frequency by the time difference between two falling edge instants when the synchronization signal across the 3.5 V threshold points. The actual synchronization threshold point is a slightly higher than the 3.5 V threshold point. The minimum synchronization pulse width is 500 ns. There is a typical 350 ns propagation delay from synchronization threshold point to the moment of output goes high and there is also a typical 300 ns propagation delay from the synchronization threshold point to the moment of crossing 3.5 V. Hence, the output goes high apparently when the sync
Table 1. Power Factor Controller Test Data
Vin (Vac) 90 110 130 150 180 190 210 230 250 Pin (W) 143.4 161.1 160.5 160.9 161.6 161.7 162.0 162.2 162.8 Vout (V) 327 373 378 382 386 387 389 391 393 Iout (mA) 400 400 400 400 400 400 400 400 400
There are two UVLO options. The device typically starts to operate when the supply voltage VCC exceeds 13.75 V for NCP1601A and 10.5 V for NCP1601B. It turns off when the supply voltage VCC goes below 9 V. An 18 V internal ESD Zener diode is connected to the VCC pin (Pin 8). Hence, the operating range is 9 V to 18 V. The 4.75 V UVLO hysteresis option of the NCP1601A and 14 mA low startup current make the self-supply design easier. The 1.5 V UVLO hysteresis option of NCP1601B makes it more flexible to match with the second-stage PWM controller biasing VCC supply voltage.
Thermal Shutdown
An internal thermal circuitry disables the circuit gate drive and then keeps the power switch off when the junction temperature exceeds 140C. The output stage is then enabled once the temperature drops below typically 95C (i.e., 45C hysteresis). The thermal shutdown is provided to prevent possible device failures that could result from an accidental overheating.
Output Drive
The output stage of the device is designed for direct drive of power MOSFET. It is capable of up to -500 mA and +750 mA peak drive current and has a typical rise and fall time of 53 and 32 ns with a 1.0 nF load.
PF 0.998 0.997 0.996 0.993 0.990 0.986 0.980 0.973 0.959
THD (%) 4 6 6 7 6 8 8 9 16
Efficiency (%) 91.2 92.6 94.2 95.0 95.5 95.7 96.0 96.4 96.6
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NCP1601A, NCP1601B
3.15 A Fuse
KBP06
450 mH / 4.5 A
MUR460
Input 90 Vac to 260 Vac
100 nF
1 mF
1 mF
680 k
68 mF 450 V
Output 390 V
680 k SPF47283900 0.1 560 k Vcc 2.2 k NCP1601B 56 SPP11N60S5
1N4934 10 k
1.5 nF
68 nF
1.5 nF
220 pF
Figure 40. 130 W Power Factor Correction Circuit
ORDERING INFORMATION
Device NCP1601AP NCP1601APG NCP1601ADR2 NCP1601ADR2G NCP1601BP NCP1601BPG NCP1601BDR2 NCP1601BDR2G Package PDIP-8 PDIP-8 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) PDIP-8 PDIP-8 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) Shipping 50 Units / Rail 50 Units / Rail 2500 Units / Tape & Reel 2500 Units / Tape & Reel 50 Units / Rail 50 Units / Rail 2500 Units / Tape & Reel 2500 Units / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NCP1601A, NCP1601B
Appendix I - Summary of Equations in NCP1601 Boost PFC
Description Boost converter Critical Mode (CRM) Discontinuous Mode (DCM)
t ) t2 Vout +1 t2 Vin
t ) t2 Vout +1 t2 Vin t1 1 ) t2
Vout * Vin + t
Vout
Input current averaged by filter capacitor Voltage for on time Vton
Vout * Vin + t
Vout t ) t2 Ipk Iin + 1 2 T
t1 1 ) t2
Ipk Iin + 2 Vton + Vcontrol LIpk t1 + , or Vin CrampVcontrol Ich
T Vton + V t1 ) t2 control LIpk t1 + , or Vin t1 + Vout * Vin CrampVcontrol T Vout Ich
MOSFET on-time t1
t1 is constant for unity PFC Vcontrol is constant for unity PFC
Switching period
t1 +
t1 (t1 + t2) is constant for unity PFC Vcontrol is constant for unity PFC
T CrampVcontrol t1 ) t2 + , or t1 Ich t1 ) t2 +
Same as CRM
CrampVcontrol Vout t1 ) t2 + , or Vout * Vin Ich LIpk Vout t1 ) t2 + Vout * Vin Vin
CrampVcontrol Vout T Vout * Vin Ich
Minimum Inductor for CRM Input impedance
V * Vin Vin 1 L u L(CRM) + out Ipk f Vout Zin + 2LIch CrampVcontrol
Same as CRM
Input power
Vac2CrampVcontrol Pin + 2LIch hV 2C V Pout + hPin + ac ramp control 2LIch Pin_max + Vac2Cramp 2LIch
Same as CRM
Output power
Same as CRM
Maximum input power when Vcontrol = 1 V
Same as CRM
Minimum ramp capacitor when Vcontrol = 1 V Control voltage Vcontrol
P Cramp u in2 @ 2LIch Vac 2LIchPin Vctrl + CrampVac2
Same as CRM
Same as CRM
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NCP1601A, NCP1601B
PACKAGE DIMENSIONS
SOIC-8 D SUFFIX CASE 751-07 ISSUE AG
-X- A
8 5
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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17
NCP1601A, NCP1601B
PACKAGE DIMENSIONS
PDIP-8 N SUFFIX CASE 626-05 ISSUE L
8
5
-B-
1 4
NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --- 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --- 10_ 0.030 0.040
F
NOTE 2
-A- L
C -T-
SEATING PLANE
J N D K
M
M TA
M
H
G 0.13 (0.005) B
M
The products described herein (NCP1601A, NCP1601B), may be covered by the following U.S. patents: 6,271,735, 6,362,067, 6,970,365. There may be other patents pending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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NCP1601A/D

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